Regviz

Espressif Systems /ESP32-S3 /SYSTEM /RSA_PD_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RSA_PD_CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S3/SYSTEM/RSA_PD_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RSA_MEM_PD)RSA_MEM_PD 0 (RSA_MEM_FORCE_PU)RSA_MEM_FORCE_PU 0 (RSA_MEM_FORCE_PD)RSA_MEM_FORCE_PD

Description

rsa memory power control register

Fields

RSA_MEM_PD

Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid.
RSA_MEM_FORCE_PU

Set 1 to force power up RSA memory, this bit has the second highest priority.
RSA_MEM_FORCE_PD

Set 1 to force power down RSA memory,this bit has the highest priority.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data